In recent years, the whirlwind of artificial intelligence technology has dramatically escalated the thirst for high computing power chips, spurring revolutionary strides in semiconductor process technology. Particularly, shrinkage technology, a marvel that boosts chip integration and performance by miniaturizing transistors, has emerged as a pivotal force in amplifying computing prowess. Yet, as these technologies edge closer to their physical brink, the latitude for enhancement narrows. Concurrently, advanced packaging technologies such as Chiplets, flaunting their innovative multi-chip integration methods, have adeptly stepped in. These methodologies not only pare down costs and power usage but also augment computing power and performance. As AI technology burgeons into maturity, these packaging marvels are now under the industry's limelight, signaling the forthcoming trajectory of chip process innovation.
With the widespread adoption of deep learning technology, AI algorithms' network structures and computational demands have surged, seemingly breathing new vigor into Moore's Law. Chen Ping, TSMC (China) Co., Ltd.'s deputy general manager, has underscored a burgeoning industry fascination with advanced process chips as the hunger for computing power intensifies. OpenAI CEO Altman's forecasts suggest an accelerated evolution of Moore's Law in the AI epoch, with transistor counts doubling every 18 months. This shift is not merely a technological leap but mirrors the escalating demand for computational might in the AI era.
Delving deeper, Chen Ping highlighted that the quest for supreme computing power doesn't halt at micro-process technology. It encompasses a spectrum of elements including novel transistors and materials, lithography technology, and a symphony of collaborative progress across design and process optimization (DTCO), circuit and architectural innovation, advanced packaging, system process optimization (STCO), and software enhancements. The harmonious advancement of these domains doesn't just propel semiconductor technology forward but opens avenues for achieving peak performance, reduced power consumption, and superior energy efficiency in chip design.
Standing at a pivotal crossroads, the evolution of semiconductor process technology is more crucial than ever. Wei Shaojun, a leading voice from the China Semiconductor Industry Association and a distinguished professor at Tsinghua University, advocates that beyond mere process shrinkage, three-dimensional hybrid bonding technology is revolutionizing chip computing power through the heterogeneous integration of memory and logic wafers. This breakthrough transcends traditional constraints, injecting a dose of flexibility and adaptability. Executed within wafer foundries, hybrid bonding streamlines process integration, significantly enhancing chip capabilities and catering to the rigorous demands of high computing power and energy efficiency in sectors like artificial intelligence.
In navigating the tumultuous seas of future computing challenges, Wei Shaojun suggests a blend of software-defined chip technology and heterogeneous stacking integration. This approach seeks a judicious balance of computing power and performance enhancements. Software-defined chips leverage hardware resources by parallelizing tasks, while heterogeneous stacking technology curtails data transmission distances and energy expenditure by tightly interweaving storage and computing units. Together, they don't just meet the stringent computing and energy efficiency demands of the AI era but also bolster chip security and reliability.
Propelled by the relentless advancement in AI and high-performance computing (HPC) realms, chiplet technology has risen as an industry linchpin. Xu Dongmei, deputy secretary-general of the China Semiconductor Industry Association and secretary-general of the Packaging and Testing Branch, notes the soaring needs for extensive data processing and complex calculations in these sectors, thereby amplifying the significance of chiplet technology. Projected to reach a staggering US$57 billion market size by 2035, the chiplet market brims with potential. However, as Chen Ping asserts, while chiplet technology flaunts robust growth prospects, it doesn't negate the need for continual advancement in process technology. Instead, an integrated approach, harnessing both chiplet and advanced process technologies, is pivotal for elevating overall chip performance.